Many USB peripherals need bulk capacitance on the input voltage supply rail greater than 10 uF but the USB 1.0, 1.1, and 2.0 specifications require that peripherals not exceed a load of 10 uF in parallel with 44 ohms. When bulk capacitance is needed in a peripheral, a power switch is utilized and turned on slowly usually 1 ms to 2 ms to minimize the inrush current. This method is useful in most applications but does not solve the problem when very large input capacitors are used because the current through the power switch increases until the current limit is invoked between 0.7 A and 1 A which exceeds the 44 ohms specification required for USB peripherals.
FIG. 1 shows a simple circuit diagram of a prior art power distribution switch 20 along with resistor 22, capacitors 24, 26, and 28, and load 30 that is used in applications to minimize inrush currents to large capacitive loads 28 (e.g. 22 uF). The power distribution switch includes input node IN, output node OUT, enable node EN, over current signal node OC, and ground node GND. Large capacitors 28 are needed in distributed power systems to minimize voltage ripple and voltage spikes associated with load transients. Adding large capacitors to a distributed power system increases the inrush currents when powering up. One method to minimize inrush current is to employ a power switch that turns on slowly as shown by equation (1).I(t)=C*dV(t)/dt  (1)
I(t) is current, C is capacitance, and dV(t)/dt is the change in voltage with respect to time.
FIG. 2 shows an internal block diagram of the prior art power distribution switch of FIG. 1. The most important internal circuit blocks include the power switch (NMOS transistor 40), driver 42, charge pump 44, and current limit circuit 46. The circuit of FIG. 2 also includes thermal sense 48, current sense 50, UVLO 52, OR gate 54, transistor 56, diode 58, enable EN, output OUT, and over current signal node OC. The NMOS transistor 40 is used because it is more cost effective than a PMOS transistor for applications requiring higher currents. Since NMOS transistors require a positive gate to source voltage, a charge pump 44 is required to boost the driver output voltage above the input voltage supply IN. Driver 42 controls turn-on and turn-off of transistor 40. A weak (low current) driver 42 and charge pump 44 are used to turn on the power switch slowly. This slow turn on time is fixed internally and varies slightly over the input voltage and temperature. This fixed turn on time is a limitation for applications that have specifications for maximum allowable inrush currents and have requirements for wide variations of bulk capacitance, such as the Universal Serial Bus (USB). The current limit is fixed at a value that is sufficiently higher than the rated load current and does not add any inrush current control.
Another prior art method for inrush current control is to use a dual current limited switch that also turns on slowly to control the inrush current. FIG. 3 shows a prior art dual current limit solution. This solution consists of a power switch 70 (with similar internal functions as the device of FIG. 2) with adjustable current limit at node ILIM and an input voltage threshold circuit 72 that is used to adjust the current limit threshold by changing the current limit adjustment resistance that is set by resistors 74 and 76, and transistor 78. This method requires prior knowledge of the components and voltage levels to function appropriately in the application.